The thickness effect of insulator layer between the semiconductor and metal contact on C-V characteristics of Al/Si3N4/p-Si device Al/Si3N4/p-Si aygıtının C-V characteristikleri üzerine metal ile yarıiletken kontak arasındaki yalıtkan tabakanın kalınlık etkisi

Öz Metal-insulator-semiconductor (MIS) structures have great interest for their good applications in electronic and optoelectronic. Their importance can be attributed that they have storage layer property, capacitance effect and high dielectric constant. For this reason, two samples of Si3N4 layers were deposited with plasma-enhanced chemical vapor deposition (PECVD) technique on p-type Si; first is about 5 nm thickness and the other is about 50 nm. The thicknesses of Si3N4 were adjusted by an ellipsometer. The thickness effect of Si3N4 layers on the Al/Si3N4/p type Si contact was studied with the capacitance-voltage (C–V) and conductance–voltage (G-V) characteristics of the contact at the frequency range from 10 kHz to 1 MHz and applied bias voltage from −5 V to +5 V at room temperature. In each contact having different insulator layers, capacitance values decreased and conductance values increased with increasing frequencies. The interface states (Nss), the effect of series resistance (Rs), barrier height (Φb) and carrier concentration (Na) were found from the capacitance-voltage (C–V) and conductance–voltage (G-V) measurements and explained in the details. To determine memristor behavior of the Al/Si3N4/p type Si contact, dual C-V and G-V measurements were performed at 500 kHz and the room temperature, and the results were compared for 5 nm and 50 nm thicknesses layers. Consequently, changing of Si3N4 layer thickness influenced properties of the contacts, and these two contacts have memristor behavior and, they can be used and improved as memory devices in the future. Metal-Yalıtkan-Yarıiletken (MIS) yapılar elektronik ve optoelektronikteki iyi uygulamalarından büyük ilgiye sahiptirler. Bu yapıların önemi tabaka depolama özelliği, kapasitans etkisi ve yüksek dileketrik sabitlerine sahip olmalarına dayandırılabilir. Bu yüzden Si3N4 tabakalı iki adet numune plazma destekli kimyasal buhar biriktirme (PECVD) yöntemiyle birinin kalınlığı 5 nm diğerinin kalınlığı 50 nm olacak şekilde p-tip Si üzerine büyütüldü. Si3N4 tabakasının kalınlığı bir elipsometreyle kontrol edildi. Al/Si3N4/p tip Si kontağın üzerine Si3N4 tabakasının kalınlık etkisi 10 kHz-1 MHz frekans değerleri için -5 V’tan +5 V voltaj aralığında yapıların kapasitans-voltaj (C–V) ve iletkenlik-voltaj (G–V) karakteristikleri ile oda sıcaklığında araştırıldı. Farklı kalınlığa sahip kontakların her bir durumda kapasitans değerlerinin artan frekansla azaldığı ve iletkenlik değerlerinin arttığı tespit edildi. Ara yüzey durumları (Nss) ve Seri direnç (Rs) etkileri, bariyer yüksekliği (Φb) ve taşıyıcı yoğunluğu (Na) kapasitans-voltaj (C–V) ve iletkenlik-voltaj (G–V) karakteristikleri karakterizasyonlardan elde edildi ve açıklandı. Ayrıca 5 nm ve 50 nm kalınlık değerindeki tabakalar için 500 kHz frekansta çift yönlü C-V ve G-V karakterizasyonlarından elde edildi ve kıyaslandı. Sonuç olarak, Si3N4 tabakasının kalınlık değişiminin kontakların özelliklerini etkilediği görüldü ve bu kontakların Memrezistör yapısına sahiptirler ve gelecekte hafıza aygıtları için kullanılabilir ve geliştirilebilirler.


Introduction
Schottky diodes and metal-semiconductor devices have good properties for using in the electronic industry such as low voltage rectifiers, inverters in high frequency, solar cells, polarity protection and freewheeling diodes [1], [2]. Past to present, schottky diodes or contacts have attracted the interest on their conduction mechanism and barrier height and, they have been mostly investigated several times by many researchers [3]- [7].
Properties of metal and semiconductor contacts can be changed by use of interfacial insulator layers [8]. SiO2, Si3N4, SnO2, TiO2 and SrTiO3 etc. are used as insulator layers between semiconductor and metal contacts and, these layers causes to deviate from the ideal structure of the contact and provide new properties to them [9].
To better understand the metal and semiconductor contacts, their conduction mechanism and barrier height should be known. There are various parameters to explain their current conduction mechanism and barrier height such as doping concentration of atoms, interface layer, interface states density, series resistance, temperature effect, applied bias voltage and homogeneity and thickness of the insulator layer. If insulator layers are ≤100 Ǻ thicknesses, they could be called a metal-insulator-semiconductor (MIS) structure [10] otherwise, they are called metal-oxide-semiconductor (MOS) structure [11]. One of most important characteristics of insulator layers in the MIS structure are having dielectric property which is resemble a capacitor. If an insulator layer in the MIS is very thin (˜30 Ǻ), electrical parameters of this structure can be determined by current-voltage (I-V) and capacitance-voltage (C-V) measurements. But the existence of more thickness insulator layer at the interface, (I-V) measurements cannot be used.
The aim of this study, to investigate Al/Si3N4/p type Si contact according to 5 nm and 50 nm insulator layer thicknesses at room temperature because of understanding changing performance and quality of these devices depending on its thicknesses.

Materials and methods
p-type Si wafers which were polished and cleaned for the deposition of the Al/Si3N4/p type Si heterojunctions have (100) orientation and 7.3 x 10 15 cm -3 carrier concentration according to manufactures specifications. The wafers were degreased consecutively in acetone and isopropyl alcohol with ultrasonic cleaner for 5 min. The degreased wafers were etched with HF:H2O (1:10) for 30 second to take out the surface damages and undesirable impurities. Before ohmic contact, the p-type Si wafers were cut into pieces of 1.0 cm length by 1.0 cm breadth. Aluminum was evaporated (thermal) on other sides of the p-type Si for the ohmic contact and the p-Si/Al were annealed at 450 °C for 3 minute in N2 ambience. The Al contacts have been formed by thermal evaporation method as points with diameter of around 1.0 mm on the front surface of the p-Si wafers. The thickness of metal coating was designated with a quartz screen positioned in close intimacy to the Si.
The insulator layers have been formed PECVD technique on p-type Si nearly 5 nm and 50 nm thicknesses. (The ratio of Si3N4 (SiH4:NH3, (185:45 sccm)). The schematic diagram of contacts could be seen in Figure 1. The C-V and G-V measurements of the diodes were performed by using HP 4192 A LF Impedance Analyzer.

Results and discussion
The C-V characteristics of having 5 and 50 nm thicknesses Al/Si3N4/p-Si contacts have been shown in Figure 2(a) and Figure2(b), respectively. It can be said that capacitance properties of two contacts affected bias voltage and frequency alterations. As shown in Figure 2(a) and Figure 2(b), capacitance values have decreased with increasing (10 kHz to 1 MHz) frequencies in the accumulation and depletion regions. These decreasing can be attributed to the interface states and interfacial native Si3N4 layers between semiconductor and metal. In the high frequencies, interface states cannot follow ac signals and this causes low capacitance values [12]. The values of capacitances have shown each frequency, changing forward to reverse bias for having 5 nm thicknesses Si3N4 layers but in having 50 nm thicknesses Si3N4 layer, there is no any capacitance peaks changing applied bias that can be attributed increasing native layer thickness 5 nm to 50 nm [11], [13].
The G-V plots of the Al/Si3N4/p type Si contacts could be seen in Figure 3 for having different thicknesses Si3N4 layers. It has shown that conductance values increased with increasing frequencies for 5 nm and 50 nm native layer thicknesses. This increasing can be ascribed not following ac signal in the high frequencies. In 5 nm thicknesses Si3N4 layer could be observed peaks in the depletion region in all frequencies and these peaks have tendency to reverse bias voltage with increasing frequency. However, in 50 nm thicknesses Si3N4 layer; there are no seeing peaks at the G-V plots. This conclusion attributed also increasing native layer effect [11], [14]. versus bias voltage plots have been displayed in Figure 4 for having 5 nm and 50 nm layer thicknesses Si3N4 insulator between the metal and semiconductor. is given depending conductance and capacitance by: in here and are measured conductance and capacitance, respectively and is angular frequency equal to 2 . Variations at values can be explained that these values deviated from ideal condition and affected from different insulator layers. As can be seen in Figure 4(a), have given a peaks definite voltage interval where interface states can follow ac signal at low frequency, but in the high frequencies, ac signal cannot be followed by interface states and, values do not exhibit peaks. Magnitudes of peaks have increased and peaks positions have changed with negative bias voltage with decreasing frequency. In Figure 4(b), it could be seen only two peaks in 10 and 20 kHz frequencies at the accumulation region, but there is no peak in the high frequencies. This can be attributed not pursuing ac signal at high frequency values and do not exhibiting peaks more insulator layers [5], [15]. C -2 -V graphs of Al/Si3N4/p type Si contacts have been given in Figure 5(a) and Figure 5(b) for having 5 nm and 50 nm insulator Si3N4 layers, respectively. As known that C -2 -V plots exhibit a straight line in a wide bias range and diffusion potential can be found extrapolation of this line to the voltage axis. Using the slope of this line can be calculated various parameters such as barrier height, fermi level and doping concentration [12]. These values have been given in Table 1 and Table 2 for 5 nm and 50 nm native layers, respectively. It can be observed that voltage axis extrapolation have changed reverse bias to forward bias by increasing thicknesses of Si3N4 layers from 5 nm to 50 nm. As can be seen at Figure 5(b), C -2 -V plots have exhibited non-linear curve tendency to high frequencies. This case can be attributed non-uniform doping or not following ac signal at high frequencies by interface states [16].  Incoherently changing for having 50 nm thicknesses layers can be attributed the distribution of particular density in interface states and interfacial layer effects [5]. Values of and could be seen in Table 1 and Table 2 in here, A is diode area, is angular frequency, and are measured conductance and capacitance, respectively. 0 is native layer capacitance obtained from below equation at accumulation region (4 V):   In Figure 7(a), values decreased with increasing frequencies then become constant nearly at high frequencies, but increasing native layers from 5 nm to 50 nm on the contacts (Figure 7(b)), values decreased at 20 kHz frequency and increased again at 50 kHz frequency then become constant to high frequencies after again decreased little. These changing in the interface states attributed not homogeny interfacial layers in the contacts for having 50 nm native layers [17], [18].
values for 5 nm and 50 nm Si3N4 layers have been tabulated for different frequencies also in Table 1 and Table 2, respectively. values can be calculated Equation (1) and versus frequency plots have been shown in Figure 8(a) and Figure  8(b) obtained this formula (Eq. 1) for strong accumulation region for 5 nm and 50 nm native layer thicknesses, respectively. It can be seen from these plots that values decreased exponentially nearly each thickness cases. In it is having 50 nm native layer thicknesses contact, there is a deviation from exponential case in the 20 kHz frequency. This condition can be attributed to inhomogeneous interface states at having more native layer thicknesses [19], [20].
It has been observed in Figure 9 that dual capacitance and conductance characteristics at 500 kHz frequencies for having 5 nm and 50 nm native insulator layer thicknesses because of investigating the memristor behavior. Memristor has low power and nonvolatile operation, variety of physical mechanisms and potentially high density, placing advanced components of future computing systems [21]. Si3N4 is commonly used memory contacts for memristive characterizations. In the capacitance-voltage measurements for having 5 nm layers contact has a peak and memory window in the strong accumulation region but 50 nm layers contact has no peak and it has memory window wide voltage range in inversion, depletion and accumulation region and dual plots of conductance-voltage have similar the C-V plots have been indicated in Figure 9. It can be said that increasing Si3N4 layers causes changing the memory window position with increasing thickness. This changing has been seen in Figure 9 to reverse bias region.
The some experimental parameters were calculated and given in Table 1 and Table 2 for having 5 nm and 50 nm native  layers contacts for various frequencies. In the Tables, values  are    Where is the efficient density of states for Si valance band and value of is 1.04 x 10 19 cm -3 . ℎ * and 0 (in here ℎ * = 0.16 0 ) are the effective masses of the electrons and halls, respectively.
values almost have increased with increasing frequencies for having 5 nm Si3N4 layers and it can be seen in Table 1. Values of obtained from having 50 nm native layers contact have decreased by increasing frequency attributing to the increasing doping concentration because of thicker native layer can be observed in Table 2 [22]. EF values of Al/Si3N4/p type Si contacts have decreased with increasing native Si3N4 layers from 5 nm to 50 nm could be seen comparing Table 1 and Table 2. This decreasing can be attributed interfacial insulator layer effects between metal and semiconductor.
∆ is the image force barrier lowering and is given by: where is the maximum electric field and calculated with: ∆ values almost has linear decreasing by increasing frequency (Table 1) ascribing lower layer effects for having 5 nm Si3N4 layers. In 50 nm, there are a lot of fluctuations (Table 2) because of imaging barrier lowering and nonhomogenous interface states [23].
Using of values, the diffusion potentials ( ) at zero bias can be found by use of below equation: After accounting of , and ∆ , the values of barrier heights (C-V) could be obtained from below relation: Calculated values of contacts have been shown in Table 1  and Table 2 for having 5 nm and 50 nm Si3N4 layers contacts, respectively. From these tables, it can be seen that there is almost regularly decreasing the values, can be ascribed lower native layers, in having 5 nm native layers between metal and semiconductor. But at having 50 nm native layers, there are many floating in barrier height values could be seen in Table 2. This case also can be based on thicker layers and inhomogeneous of interface states or interfacial layer effects [23].

Conclusions
The thickness layer effect of Si3N4 insulator layer of the Al/Si3N4/p-Si contacts were investigated with capacitance-voltage (C-V) and conductance-voltage (G−V) characteristics of the structures at various frequencies and applied bias voltage ranges at room temperature. Changing the Si3N4 layer thickness has affected C-V and G-V characteristics of the contact. Capacitance values decreased and conductance values increased with increasing frequencies for 5 and 50 nm Si3N4 layers contacts. There are peaks all frequencies in having 5 nm native layers, but adding 50 nm insulator layer between the metal and semiconductor has not shown any peaks. The interface states ( ) values have decreased with increasing frequency for contacts having various layers thicknesses. The diode parameters such as series resistance ( ), barrier height ( ) and carrier concentration ( ) were plotted versus frequency. It can be said that these and other some accounted parameters were affected having different native layers thicknesses. It was also measured and compared C-V and G−V characterizations dual measurement at 500 kHz in room temperature for 5 nm and 50 nm thickness layers. These contacts have similarly memristor structure and can be used as memory devices.